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Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL
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Two LVPECL Outputs
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Maximum Clock Frequency: 2 GHz
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Maximum Core Current Consumption: 33 mA
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Very Low Additive Jitter: <100 fs, RMS in 10-kHz to 20-MHz Offset Range
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2.375-V to 3.6-V Device Power Supply
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Maximum Propagation Delay: 450 ps
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Maximum Output Skew: 10 ps
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LVPECL Reference Voltage, VAC_REF, Available for Capacitive-Coupled Inputs
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Industrial Temperature Range: –40°C to 85°C
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Supports 105°C PCB Temperature (Measured at Thermal Pad)
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Available in 3-mm × 3-mm QFN-16 (RGT) Package
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ESD Protection Exceeds 2 kV (HBM)
2 Applications
3 Description
The CDCLVP1102 is a highly versatile, low additive jitter buffer that can generate two copies of LVPECL clock outputs from one LVPECL, LVDS, or LVCMOS input for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 10 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP1102 clock buffer distributes a single clock input (IN) to two pairs of differential LVPECL clock outputs (OUT0, OUT1) with minimum skew for clock distribution. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP1102 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP1102 is characterized for operation from –40°C to 85°C and is available in a QFN-16, 3-mm × 3-mm package.
Device Information
